最近一直在做一些小模块的验证，之前都是在用现成的环境修修改改。
写一个纯sv的环境；
首先是harness；
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module harness
bit clk;
bit rst_n;
w_inf inf(bit clk,bit rst_n);
tc test();
dut dut(
clk (inf.clk),
rst_n(inf.rst_n),
a (inf.a),
b (inf.b)
);
initial begin
clk = 0;
forever #0.5ns clk = ~clk;
end
endmodule
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之后是interface；
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| interface w_inf(bit clk,bit rst_n);
logic a;
logic b;
clocking drv_cb @(posedge clk);
inout a;
inout b;
endclocking
endinterface
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之后定义一个transaction；
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| class transaction
bit a;
bit b;
endclass
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之后是定义一个sequence；
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class w_sequence
bit a[$];
virtual w_inf bus;
extern virtual new(w_inf inf);
extern virtual task tx_process();
extern virtual task rx_process();
extern virtual function chk_ans();
endclass
task w_sequence::txprocess();
endtask
task w_sequence::rxprocess();
endtask
function w_sequence::new(w_inf inf);
bus = inf;
endtask
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最后定义一下tc;
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| program tc;
sequence seq;
w_inf inf;
inf = harness.inf;
initial begin
seq = new(inf);
fork
begin
seq.tx_process();
end
begin
seq.rx_process();
end
begin
harness.rst_n = 0;
repeat(4)@(posedge vif.clk);
harness.rst_n = 1;
repeat(100)@(posedge vif.clk);
$finish;
end
join
end
endprogram
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